Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional analog phase locked loop circuit 100 according to prior art. The analog phase locked loop circuit 100 consists of a phase frequency detector 10, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, and a frequency divider 50. A reference signal (Sref) 11 with a reference frequency (Fref) is generated by a reference oscillator (not shown), and the reference signal (Sref) 11 and a frequency divided signal (Sfd) 52 are simultaneously inputted to the phase frequency detector 10. The phase frequency detector 10 is capable of detecting a phase difference as well as a frequency difference between the reference signal (Sref) 11 and the frequency divided signal (Sfd) 52, and then outputs a phase difference signal 12 to the charge pump 20. Afterwards, the charge pump 20 generates an output current 22 related to the phase difference signal 12 to the loop filter 30 according to the phase difference signal 12. The loop filter 30 is a low pass filter (LPF) composed of a resistor (R) and a capacitor (C). In theory, the loop filter 30 is able to average the output current 22 and transform it into a voltage controlled signal 32 to the voltage controlled oscillator 40. The voltage controlled oscillator 40 is able to generate an output voltage controlled oscillating signal (SVCO) 42 according to the voltage controlled signal 32, wherein the output voltage controlled oscillating signal (SVCO) 42 has a voltage controlled frequency (FVCO). The frequency divider 50 is capable of receiving the output voltage controlled oscillating signal (SVCO) 42 and dividing the output voltage controlled oscillating signal (SVCO) 42 by an integer N to generate the frequency divided signal (Sfd) 52 to be inputted to the phase frequency detector 10. Therefore, an equation FVCO=N*Fref can be obtained by the analog phase locked loop circuit 100.
Since the phase difference signal 12, the output current 22, and the voltage controlled signal 32 are all analog signals, the phase locked loop circuit 100 including the abovementioned elements is called as an analog phase locked loop circuit.
In addition, please refer to FIG. 2, which is a diagram illustrating an s-domain model of an analog phase loop circuit. A function for the phase frequency detector combined with charge pump 25 is represented by ICP/2π; a function for the loop filter 30 is represented by Z(s); a function for the voltage controlled oscillator 40 is represented by KVCO/s; and a function for the frequency divider 50 is represented by 1/N; wherein ICP represents the output current 22 of the charge pump 20, KVCO represents a tuning sensitivity of the voltage controlled oscillator 40.
The conventional analog phase locked loop circuit has the following disadvantages: design modifications are required with different processes, and the voltage controlled oscillator 40 is sensitive to noises. In order to solve such disadvantages of the analog phase locked loop circuit, an all digital PLL has already been developed.
Compared with the analog phase locked loop circuit, the signals delivered between the components of the all digital PLL are all digital values. For this reason, the phase or transmission path correction of the all digital PLL won't be interfered by noises, and the all digital PLL can directly follow the evolution of the contracting process.
Please refer to FIG. 3A. FIG. 3A is a diagram illustrating a conventional all digital phase locked loop circuit 200 according to prior art. The all digital phase locked loop circuit 200 includes a phase frequency detecting and time-to-digital circuit 125, a digital controller 130, a delta-sigma modulator 135, a digital controlled oscillator 140, and a frequency divider 150. A reference signal (Sref) 111 having a reference frequency (Fref) is generated by a reference oscillator (not shown), and the reference signal (Fref) 111 as well as a frequency divided signal (Sfd) 152 are simultaneously inputted to the phase frequency detecting and time-to-digital circuit 125. The phase frequency detecting and time-to-digital circuit 125 is capable of detecting a phase difference and a frequency difference between the reference signal (Sref) 111 and the frequency divided signal (Sfd) 152 and generating a phase difference value 122 in response to them. After that, the digital controller 130 receives and processes the phase difference value 122 to generate a control value 132. The delta-sigma modulator 135 modulates the received control value 132 and generates a modulated control value 134 in response to the control value 132. The digital controlled oscillator 140 generates an output oscillating signal (SDCO) 142 according to the modulated control value 134, wherein the output oscillating signal (SDCO) 142 has a digital controlled frequency (FDCO). The frequency divider 150 is capable of receiving the output oscillating signal (SDCO) 142 and dividing the output oscillating signal (SDCO) 142 by an integer N so as to generate the frequency divided signal (Sfd) 152 to be inputted to the phase frequency detecting and time-to-digital circuit 125. Therefore, an equation FDCO=N*Fref can be obtained by the all digital phase locked loop circuit 200. Please note that the digital controller 130 of the all digital phase locked loop circuit 200 can be simulated as a digital loop filter, and the delta-sigma module 135 is used for increasing a resolution of the voltage controlled frequency FVCO when it changes.
All of the phase difference value 122, the control value 132, and the modulated control value 134 are digital values, so that the phase locked loop circuit 200 composed of the abovementioned components is called as an all digital phase locked loop circuit.
Please refer to FIG. 3B. FIG. 3B is a diagram illustrating a conventional phase frequency detecting and time-to-digital circuit according to prior art. This phase frequency detecting and time-to-digital circuit includes n inverters 201˜20n, n D-type flip-flops 211˜21n, and a pseudo-thermometer-code edge detector 230. The n inverters 201˜20n are cascaded into a delay chain, wherein an input terminal of the first inverter 201 is used for receiving the frequency divided signal (Sfd), and a propagation delay of each inverter is represented by ΔTDC. Each of the D-type flip-flops 211˜21n has a data input terminal (D) respectively coupled to the corresponding output terminal inv1˜invn of the inverters 201˜20n, and each of the D-type flip-flops 201˜20n has a clock input terminal coupled to the reference signal (Sref). Moreover, an inverted output terminal ( Q) of the D-type flip-flops with an odd number is coupled to the pseudo-thermometer-code edge detector 230, and a non-inverted output terminal (Q) of the D-type flip-flops with an even number is coupled to the pseudo-thermometer-code edge detector 230. As a result, the n D-type flip-flops 211˜21n are capable of outputting a signal of n-bits Q[1]˜Q[n].
As can be known from FIG. 3B, the delay chain composed of the n inverters 201˜20n is capable of generating a group of delayed signals inv1˜invn of the frequency divided signal (Sfd). After the time difference between the frequency divided signal (Sfd) and the reference signal (Sref) is sampled, the phase relationship between the frequency divided signal (Sfd) and the reference signal (Sref) can be obtained.
For example, please refer to FIG. 3C. FIG. 3C is a diagram illustrating the signals of the phase frequency detecting and time-to-digital circuit. Take eight inverters 201˜208 as the example, wherein the propagation delay of each inverter is represented by Δt. Therefore, eight delayed signals inv1˜inv8 of the frequency divided signal (Sfd) can be obtained. In addition, assume that the delayed signals inv1˜inv8 are sampled at the rising edge of the reference signal (Sref), and thus we can obtain that Q[1:8]=[100111100]. Therefore, we can make sure that the time difference between the frequency divided signal (Sfd) and the reference signal (Sref) is equal to the total propagation time of the six inverters 201˜206. The pseudo-thermometer-code edge detector 230 is capable of receiving the signal of 8-bits Q[1]˜Q[8] and transforming it into the phase difference value 122 according their sampled positions. In this case, the resolved phase difference value 122 is equal to 6.
Please refer to FIG. 3D. FIG. 3D is a diagram illustrating a digital controller. The digital controller consists of a proportional control unit 240, an integrating control unit 242, a first adder 244, a second adder 246, and a delay unit (Z−1) 248. The proportional control unit 240 is capable of receiving the phase difference value 122 and multiplying the phase difference value 122 by the numeric of KP so as to output a proportional value 241. The integrating control unit 242 is capable of receiving the phase difference value 122 and multiplying the phase difference value 122 by the numeric of KI so as to output an integral value 243. The delay unit (Z−1) 248 is capable of receiving the control value 132 and outputting a delay value 249. The first adder 244 adds the delay value 249 and the integral value 243 together so as to get a first value 245. The second adder 246 adds the first value 245 and the proportional value 241 together so as to get the control value 132. From all the considerations above, the digital controller can be simulated as a digital loop filter.
Furthermore, the delta-sigma modulator 135 is used for increasing a resolution of the voltage controlled frequency FVCO when it changes. Since the control value 132 represents an integer, the variations of the control value 132 are all integer variations. For example, the control value 132 can be increased from an integer 5 (0101) into another integer 6 (0110); or it can be decreased from an integer 5 (0101) into another integer 4 (0100). The delta-sigma modulator 135 can modulate the control value 132, so that the integer variations of the control value 132 are changed into fractional variations. That is to say, the modulated control value 134 can be increased from an integer 5 into 5.1, 5.2, . . . , and so on; or it can be decreased from an integer 5 into 4.9, 4.8, . . . , and so on. For this reason, the modulated control value 134 is able to increase the resolution of the voltage controlled frequency FVCO when it changes. However, the delta-sigma modulator 135 has been widely applied to the phase locked loop circuit, and further description is omitted herein.
Please refer to FIG. 3E. FIG. 3E is a diagram illustrating a first kind of digital controlled oscillator. The digital controlled oscillator consists of a bias current source (IBIAS) 252, a digital-to-analog converting matrix 254, a current-to-voltage converter 256, and a voltage controlled oscillator 258. The bias current source (IBIAS) 252 is capable of providing a plurality of current sources with different currents to the digital-to-analog converting matrix 254. The digital-to-analog converting matrix 254 receives the modulated control value 134, and divides the modulated control value 134 into a row value and a column value for enabling/disabling a number of current sources among the bias current source 252. The enabled current sources are aggregated into an analog current signal 255 to be inputted to the current-to-voltage converter 256. The current-to-voltage converter 256 can further convert the analog current signal 255 into an analog voltage signal 257 to be inputted to the voltage controlled oscillator 258, so as to generate an output oscillating signal (SDCO) 142.
Please refer to FIG. 3F. FIG. 3F is a diagram illustrating a second kind of digital controlled oscillator. The digital controlled oscillator consists of a bias current source (IBIAS) 252, a digital-to-analog converting matrix 254, and a current controlled oscillator 259. The bias current source 252 is capable of providing a plurality of current sources with different currents to the digital-to-analog converting matrix 254. The digital-to-analog converting matrix 254 receives the modulated control value 134, and divides the modulated control value 134 into a row value and a column value for enabling/disabling a number of current sources among the bias current source 252. The enabled current sources are aggregated into an analog current signal 255 to be inputted to the current controlled oscillator 259. The current controlled oscillator 259 can further convert the analog current signal 255 into the output oscillating signal (SDCO) 142.
Moreover, please refer to FIG. 4. FIG. 4 is a diagram illustrating an s-domain model of a conventional all digital phase locked loop circuit. A function for the phase frequency detecting and time-to-digital circuit 125 is represented by [Tref/2π]*1/ΔTDC; a function for the loop filter 130 is represented by H(s); a function for the voltage controlled oscillator 140 is represented by KDCO/s; and a function for the frequency divider 150 is represented by 1/N; wherein Tref represents a period of the reference signal (Sref) and is equal to (1/Fref), ΔTDC is a propagation delay of the inverter, and KDCO represents a tuning sensitivity of the digital controlled oscillator 140.
Regardless of the analog phase locked loop circuit or the all digital phase locked loop circuit, those skilled in the art should maintain a loop dynamics and a damping factor (ζ) at a fixed value as far as possible. The loop dynamics is equal to ωn/ωref, wherein ωn represents the loop bandwidth, and ωref represents the loop operating speed (i.e., 2πFref).
In a 2nd order analog phase locked loop circuit,
            ω      n        =                                        I            CH                    ·                      K            VCO                                    N          ·          C                      ,and the damping factor is represented by an equation:
  ζ  =            1      2        ⁢                                        1            N                    ·                      I            CH                    ·                      K            VCO                    ·                      R            2                    ·          C                    .      The symbol “ICH” represents the output current of the charge pump, the symbol “KVCO” represents a tuning sensitivity of the voltage controlled oscillator, the symbol “N” represents the divisor of the frequency divider, the symbol “C” represents the capacitance of the loop filter, and the symbol “R” represents the resistance of the loop filter.
Similarly, in an all digital phase locked loop circuit,
            ω      n        =                                        1                                          Δ                TDC                            ·                              F                ref                                              ·                      K            DCO                                    N          ·                      1                                          K                I                            ·                              F                ref                                                          ,and the damping factor is represented by an equation:
  ζ  =                    K        p            2        ⁢                                        1            N                    ·                      1                                          Δ                TDC                            ·                              F                ref                                              ·                      K            DCO                    ·                      1                                          K                I                            ·                              F                ref                                                        .      The symbol “ΔTDC” represents the propagation delay of the inverter, the symbol “KDCO” represents a tuning sensitivity of the voltage controlled oscillator, the symbol “N” represents the divisor of the frequency divider, the numeric of KP is provided by the proportional control unit 240, the numeric of KI is provided by the integrating control unit 242, and the symbol “Fref” means the reference frequency.
However, in order to provide an adjustable digital controlled frequency (FDCO) with a large range, the loop dynamics and the damping factor of the conventional all digital phase locked loop circuit are unable to be maintained at a fixed value. In addition, owing to the changes of the process, the supply voltage, and the temperature, the inverters of the conventional phase frequency detecting and time-to-digital circuit 125 will generate an error substantially equaling four times of ΔTDC, and the digital controlled oscillator 140 will generate a variation substantially equaling three times of KDCO. Moreover, the numeric of KP provided by the proportional control unit 240 and the numeric of KI provided by the integrating control unit 242 must be controlled by a trimming register. Since the variations of the numeric of KP as well as the numeric of KI exceed 2nd orders (i.e., 100 times), the design for the trimming register will occupy a large layout area in the all digital phase locked loop circuit.
Please refer to FIG. 5A together with FIG. 5B. FIG. 5A and FIG. 5B are variation diagrams of a numeric of KP and a numeric of KI in the all digital phase locked loop circuit with a fixed reference signal. As can be known from FIG. 5A, when the digital controlled frequency (FDCO) varies from 6 MHz to 400 MHz, the numeric of KP varies from 2−12 to 2−5 in order to maintain the loop parameters as ζ=1 and ωn/ωref=1/50. Similarly, when the digital controlled frequency (FDCO) varies from 6 MHz to 400 MHz, the numeric of KI varies from 2−16 to 2−9. For these reasons, the trimming register must store the corresponding numeric of KP and the corresponding numeric of KI when the digital controlled frequency (FDCO) changes. The abovementioned embodiment is presented for illustrating a condition with a fixed reference frequency. If the reference frequency changes, more trimming registers are required for storing the numeric of KP and the numeric of KI.